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| irl530ns/l hexfet ? power mosfet pd - 91349c l advanced process technology l surface mount (irl530ns) l low-profile through-hole (irl530nl) l 175c operating temperature l fast switching l fully avalanche rated absolute maximum ratings fifth generation hexfets from international rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the d 2 pak is a surface mount power package capable of accommodating die sizes up to hex-4. it provides the highest power capability and the lowest possible on- resistance in any existing surface mount package. the d 2 pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0w in a typical surface mount application. the through-hole version (irl530nl) is available for low- profile applications. description v dss =100v r ds(on) = 0.10 w i d = 17a 2 d pak to-262 parameter typ. max. units r q jc junction-to-case CCC 1.9 r q ja junction-to-ambient ( pcb mounted,steady-state)** CCC 40 thermal resistance c/w parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v ? 17 i d @ t c = 100c continuous drain current, v gs @ 10v ? 12 a i dm pulsed drain current ?? 60 p d @t a = 25c power dissipation 3.8 w p d @t c = 25c power dissipation 79 w linear derating factor 0.53 w/c v gs gate-to-source voltage 20 v e as single pulse avalanche energy ?? 150 mj i ar avalanche current ? 9.0 a e ar repetitive avalanche energy ? 7.9 mj dv/dt peak diode recovery dv/dt ?? 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c s d g 11 1/09/04
irl530ns/l parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode) ?? CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 9.0a, v gs = 0v ? t rr reverse recovery time CCC 140 210 ns t j = 25c, i f = 9.0a q rr reverse recovery charge CCC 740 1100 nc di/dt = 100a/s ?? t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) ? starting t j = 25c, l = 3.7mh r g = 25 w , i as = 9.0a. (see figure 12) ? repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) notes: ? i sd 9.0a, di/dt 540a/s, v dd v (br)dss , t j 175c ? pulse width 300s; duty cycle 2%. ? uses irl530n data and test conditions ** when mounted on 1" square pcb ( fr-4 or g-10 material ). for recommended soldering techniques refer to application note #an-994. source-drain ratings and characteristics s d g 17 60 a parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 100 CCC CCC v v gs = 0v, i d = 250a d v (br)dss / d t j breakdown voltage temp. coefficient CCC 0.122 CCC v/c reference to 25c, i d = 1ma ? CCC CCC 0.100 v gs = 10v, i d = 9.0a ? CCC CCC 0.120 w v gs = 5.0v, i d = 9.0a ? CCC CCC 0.150 v gs = 4.0v, i d = 8.0a ? v gs(th) gate threshold voltage 1.0 CCC 2.0 v v ds = v gs , i d = 250a g fs forward transconductance 7.7 CCC CCC s v ds = 50v, i d = 9.0a ? CCC CCC 25 v ds = 100v, v gs = 0v CCC CCC 250 v ds = 80v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 na v gs = 16v gate-to-source reverse leakage CCC CCC -100 v gs = -16v q g total gate charge CCC CCC 34 i d = 9.0a q gs gate-to-source charge CCC CCC 4.8 nc v ds = 80v q gd gate-to-drain ("miller") charge CCC CCC 20 v gs = 5.0v, see fig. 6 and 13 ?? t d(on) turn-on delay time CCC 7.2 CCC v dd = 50v t r rise time CCC 53 CCC i d = 9.0a t d(off) turn-off delay time CCC 30 CCC r g = 6.0 w, v gs = 5.0v t f fall time CCC 26 CCC r d = 5.5 w, see fig. 10 ?? between lead, CCC CCC and center of die contact c iss input capacitance CCC 800 CCC v gs = 0v c oss output capacitance CCC 160 CCC pf v ds = 25v c rss reverse transfer capacitance CCC 90 CCC ? = 1.0mhz, see fig. 5 ? electrical characteristics @ t j = 25c (unless otherwise specified) i gss i dss drain-to-source leakage current r ds(on) static drain-to-source on-resistance l s internal source inductance 7.5 ns nh a irl530ns/l fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics 0.1 1 10 100 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source volta g e ( v ) ds a 20 s pulse w idth t = 25c j vgs top 15v 12v 10v 8.0v 6.0v 4.0v 3.0v bottom 2.5v 2.5v 0.1 1 10 100 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source volta g e ( v ) ds a 20 s pulse w idth t = 175c vgs top 15v 12v 10v 8.0v 6.0v 4.0v 3.0v bottom 2.5v 2.5v j 0.1 1 10 100 2345678910 t = 25c j gs v , gate-to-source volta g e (v) d i , drain-to-source current (a) v = 50v 20s pulse w idth t = 175c j a ds 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 j t , junction temperature (c) r , drain-to-s ource o n resistance ds(on) (n orm alized) v = 10v gs a i = 15 a d irl530ns/l fig 7. typical source-drain diode forward voltage fig 5. typical capacitance vs. drain-to-source voltage fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage 0 3 6 9 12 15 0 1020304050 q , total g ate char g e ( nc ) g v , g ate-to-source voltage (v) gs ?v = 80v ?v = 50v v = 20v ds ds ds a for test circuit? s ee figure 13 i = 9.0 a d 1 10 100 0.4 0.6 0.8 1.0 1.2 1.4 t = 25c j v = 0v? gs v , source-to-drain voltage (v) i , reverse drain current (a) sd sd a t = 175c j 1 10 100 1000 1 10 100 1000 v , drain-to-source volta g e ( v ) ds i , drain current (a) o peration in this are a limited by r d ds(on) 10s 100s 1ms 10ms a ?t = 25c ?t = 175c sin g le p u ls e c j 0 200 400 600 800 1000 1200 1400 1 10 100 c, capacitance (pf) ds v , drain-to-source volta g e ( v ) a v = 0v , f = 1mhz c = c + c , c shorte d c = c c = c + c gs iss gs gd ds rss gd oss ds gd c? iss c? oss c? rss irl530ns/l 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) fig 9. maximum drain current vs. case temperature fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms fig 11. maximum effective transient thermal impedance, junction-to-case v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 5.0v + - v dd 25 50 75 100 125 150 175 0 5 10 15 20 t , case temperature ( c) i , drain current (a) ? c d irl530ns/l fig 12a. unclamped inductive test circuit fig 12b. unclamped inductive waveforms v ds l d.u.t. v dd i as t p 0.01 w r g + - t p v ds i as v dd v (br)dss 5.0 v q g q gs q gd v g charge fig 13a. basic gate charge waveform d.u.t. v ds i d i g 3ma v gs .3 m f 50k w .2 m f 12v current regulator same type as d.u.t. current sampling resistors + - fig 12c. maximum avalanche energy vs. drain current fig 13b. gate charge test circuit 5.0 v 0 50 100 150 200 250 300 350 25 50 75 100 125 150 175 j e , single pulse avalanche energy (mj) as a startin g t , junction temperature ( c ) v = 25v i to p 3.7a 6.4a bottom 9.0a dd d irl530ns/l p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit ? ? ? r g v dd dv/dt controlled by r g driver same type as d.u.t. i sd controlled by duty factor "d" d.u.t. - device under test d.u.t circuit layout considerations low stray inductance ground plane low leakage inductance current transformer ? * !" !#! $$ ! ! !" # $ !" for gb production to-262 package outline to-262 part marking information igbt 1- gate 2- collec- tor dimensions are shown in millimeters (inches) 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 4.72 (.136) 4.52 (.178) 24.30 (.957) 23.90 (.941) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 13.50 (.532) 12.80 (.504) 330.00 (14.173) max. 27.40 (1.079) 23.90 (.941) 60.00 (2.362) min. 30.40 (1.197) max. 26.40 (1.039) 24.40 (.961) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. data and specifications subject to change without notice. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 01/04 note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ |
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